lithography

Virtual Lithography Tool Targets EUV, Double Patterning Lithography Challenges

lithography tool, the PROLITH X3.1, which enables researchers at leading-edge chipmakers, consortia and equipment makers to quickly and cost-effectively troubleshoot challenging issues in EUV and double patterning lithography (DPL) processes, including... EDN Asia
Component / Hardware / Interconnect - Capital Equipment

Nano-imprint Makes its Mark

lithography (NIL) to make experimental memory chips with tiny electrical pathways less than half that size. "We're now using imprint lithography to routinely make real, operating circuits with a half-pitch [width] of 30 nanometers," says Williams, a senior... EDN Asia
Semiconductors

Cadence Litho-Aware DFM Tool Aims to Improve Yield

lithography to 45nm processes and beyond, San Jose-based EDA market leader Cadence Design Systems made strides in improving manufacturing yield with its Virtuoso Resolution Enhancement Technology (RET) suite of tools, meant to integrate lithography awareness... EDN Asia
EDA

Nano-imprint makes its mark

lithography (NIL) to make experimental memory chips with tiny electrical pathways less than half that size. "We're now using imprint lithography to routinely make real, operating circuits with a half-pitch [width] of 30 nanometers," says Williams, a senior... EDN Asia
Management

Lam Research Releases Post-lithography Pattern Enhancement System

lithography pattern enhancement system, designed for cost-effective production of next-generation feature sizes using current lithography technology. Employing a proprietary plasma-assisted process, the new system delivers controlled photoresist hole... EDN Asia
Capital Equipment

TSMC Joins CEA-Leti Program on Multiple E-Beam Lithography

lithography for IC manufacturing. Intended to operate for three years, this program allows companies to assess a maskless lithography infrastructure for IC manufacturing and use MAPPER Technology as a solution towards high throughput. It covers a global... EDN Asia
Semiconductors - Processors & Tools

IMEC reports progress in Advanced Lithography Program

lithography program to the 32nm half pitch node, IMEC reports progress on high-index 193nm immersion lithography, double-patterning schemes for 193nm water-based immersion lithography and extreme UV (EUV) lithography. "Over the last year, we've made... EDN Asia
Digital ICs - Processors & Tools

TEL and IMEC Extend Lithography Collaboration

lithography technologies with IMEC, an independent research center in nanoelectronics and nanotechnology. TEL will install two 300mm Clean Track systems at IMEC in 2006. The coater/developers will be used for research into EUV Lithography and Hyper NA... EDN Asia
Component / Hardware / Interconnect - Digital Den - Digital ICs

Photronics Concentrates on Imprint Template Tech

lithography, specifically working on the related template technology. "One concern with bringing nano-imprint lithography to volume production is having access to an adequate template supply," Christopher Progler, Photronics CTO, said in a statement.... EDN Asia
Digital Den

Magnification Ratio Change Unlikely for 32 nm Half-Pitch

lithography mask standard of 4X magnification with 26 mm field size is likely resilient enough to take the semiconductor industry to the 32 nm half-pitch technology generation, leading equipment suppliers and manufacturers concluded at a recent SEMATECH-sponsored... ECN Asia
Integrated Circuits & Semiconductors

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